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CXL
Emerging Memories
External Memory
Use Case
Hardware Eng.
Memory Systems Eng.
Software Eng.
Systems Architecture
Moderator

Author:

Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

Camberley Bates

Managing Director & Analyst
Evaluator Group

www.evaluatorgroup.com

Camberley is responsible for corporate leadership and as an analyst, tracks go-to-market and channel strategies. She brings over 20 years of executive experience leading sales and marketing teams at VERITAS, GE Access, and EDS. Her unique 360-degree view of addressing challenges and delivering solutions was achieved from crossing the boundary of sales and channel engagement with large enterprise vendors and her own 100-person IT services firm.

Before joining Evaluator Group in 2009, she provided Global 250 startups with go-to-market strategies at her consulting firm, Bates Strategy Group. She also created new market category “MAID” as Vice President of Marketing at COPAN and led a worldwide marketing team including channels as a VP at VERITAS. At GE Access, a $2B distribution company, she served as VP of a new division and succeeded in growing the company from $14 to $500 million. Camberley began her career at IBM in sales and management.

She holds a BS degree in International Business from California State University – Long Beach and executive certificates from Wellesley and Wharton School of Business.

 

Panellists

Author:

Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

Samir Rajadnya

Principal Architect
Microsoft

Samir Rajadnya is currently a Principal Architect in Microsoft's Azure Hardware Architecture team, which is responsible for long-range technology pathfinding for future Azure Cloud systems. Within AHA, Samir is part of a team responsible for future memory systems. This team investigates future architecture directions for Azure and serves as the primary architecture contact point in technical relationships with compute, memory, and device partners.

Prior to joining Microsoft, Samir spent many years innovating in memory, storage, and networking. Samir was key architect to productize 3DXP technology at Micron, architect, and designer at disruptive storage startup DSSD. Samir was SOC architect and designer at Juniper Networks, Netronome and Intel.

Samir has served as part of multiple industry standards bodies throughout his career, including CXL and CCIX.

Samir received his Master’s in Electrical Engineering from Indian Institute of Technology Bombay.

Specialties: Computer architecture, memory technologies, storage technologies, SOC architecture

 

 

Author:

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

Bill Gervasi

Memory Technology Analyst
Discobolus Designs

Bill Gervasi joined Intel in 1976 in the computer systems group manufacturing department, eventually leaving Intel in 1995. During that period, the computer industry changed from computers that filled rooms the size of basketball courts to desktop and laptop form factors in nearly every home in the world.

Since then, Bill specialized in the computer memory technology arena, getting involved in international standards and battles for global dominance for this key part of computer systems. As a chairman of the JEDEC standards organization, he has had a role in paving the memory industry roadmap, and contributed to spreading these standards to the world including engagement with foreign governments. Bill is a public speaker in this niche, generating both excitement and controversy with his aggressive vision for change and progress.

Bill is an incurable practical joker who thrives on making people laugh (or periodically grimace), and his years in the nascent computer industry are polka dotted with gags on unsuspecting co-workers. Bill’s eclectic background also includes years as a published food critic, and fortunately even more years as an aerobics fitness instructor, apparently to burn off the calories consumed while reviewing restaurants. He lives with his wife in Orange County, California.

Bill makes the best coffee in the world, in case you wondered.

Author:

Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

Ahmad Danesh

Associate Vice President, Product Management
Astera Labs

Ahmad Danesh is a strategic marketing and product management director with 15+ years’ experience in semiconductor, software, storage, server and data center industries. He is focused on driving product strategy for new market segments by translating data center bottlenecks into profitable and competitive hardware and software product roadmaps using Compute Express Link™ technology.


Ahmad serves as Sr. Director of Product Management at Astera Labs and has been an active member of the CXL™ Consortium's Marketing Work Group since inception in 2019.

Author:

Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Mahesh Wagh

Senior Fellow & Server System Architect
AMD

Mahesh Wagh is AMD Sr. Fellow, Server System Architect in the AMD Datacenter System Architecture and Engineering team, developing world-class products and solutions around EPYC processors.

Prior to joining AMD, Mahesh was a Senior Principal Engineer at Intel corporation, focusing on IO and SoC architecture and related technology developments. He has broad experience in chipset and IO architecture, design and validation on both Server and Client platforms.

Some of Mahesh´s significant achievements include the enhancements to PCI Express Architecture and Specification, leading CPU IO domain architecture and IO IP architecture & Interfaces and leading AMD´s Compute Express Link (CXL) efforts.

Author:

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

Siamak Tavallaei

Advisor to the Board
CXL Consortium

Siamak Tavallaei has recently served as the CXL Consortium President and Chief Systems Architect at Google Cloud. Currently he is the CXL Advisor to the Board and the Incubation Committee (IC) member for OCP Server Project where he drives the architecture and productization of CXL-enabled solutions. His current focus is the system optimization for large-scale, mega-datacenters for general-purpose and tightly-connected, accelerated machines built on co-designed hardware, software, security, and management.  In 2019, he joined CXL effort as a founding member where he first served as co-chair of Technical Task Force (TTF) and as the CXL President in 2021. In 2016, he joined OCP as a co-lead of Server Project and now is the Incubation Committee (IC) member where he drives open-sourced modular design concepts for integrated hardware/software solutions (OAI, DC-SCM, DC-MHS, and DC-Stack).  His experiences as Chief Systems Architect at Google, Principal Architect at Microsoft Azure, Distinguished Technologist at HP, and Principal Member of Technical Staff at Compaq along with his contributions to industry collaborations such as EISA, PCI, InfiniBand, and PCIe give Siamak a broad understanding of requirements and solutions for the Enterprise, Hyperscale, and Edge datacenters for industry-wide initiatives.

CXL
Emerging Memories
External Memory
Systems Design
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

Matthew Burns

Technical Marketing Manager
Samtec

Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 20+ years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Mr. Burns holds a B.S. in Electrical Engineering from Penn State University.

Innovation excites us and unlocks business value but unless it inherently scales profitably, you could be stuck at a dead-end. This talk looks at NVDIMM-N as a cautionary tale of commercialization pitfalls that kill innovative technologies. How can you analyse a technology not just for the value it unleashes but also for its long-term commercial viability? How is CXL different? What types of CXL implementations should you consider and which should you be wary of?

 

CXL
Emerging Memories
Use Case
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Keith Winkeler

VP of Engineering, PowerEdge & Core Compute Platforms
Dell Technologies

Keith Winkeler is VP of Engineering, PowerEdge & Core Compute Platforms at Dell Technologies. Keith is an accomplished and collaborative executive with 30 years of demonstrated excellence in building and leading high performance global organizations responsible for architectural definition, development and delivery of industry leading HW/SW products. His proven strengths include talent management and development, organizational design, matrixed and global teams, ODM partner leadership and value chain management.

Keith Winkeler

VP of Engineering, PowerEdge & Core Compute Platforms
Dell Technologies

Keith Winkeler is VP of Engineering, PowerEdge & Core Compute Platforms at Dell Technologies. Keith is an accomplished and collaborative executive with 30 years of demonstrated excellence in building and leading high performance global organizations responsible for architectural definition, development and delivery of industry leading HW/SW products. His proven strengths include talent management and development, organizational design, matrixed and global teams, ODM partner leadership and value chain management.

The leading companies at every level of the data center value chain, from IP, chips, platforms, system OEMs to hyperscalers, are coalescing around CXL technology as a path to revolutionize the data center. With workload demands increasing rapidly, the need for more memory bandwidth and capacity continues to rise. Memory is of critical importance, and its share of the server bill of materials (BoM) continues to grow. Making the best use of vital memory resources is an imperative. With CXL technology, the industry is pursuing tiered-memory solutions that can break through the memory bottleneck while at the same time delivering greater efficiency and improved TCO. Ultimately, CXL technology can support composable architectures that match the amount of compute, memory and storage in an on-demand fashion to the needs of a wide range of advanced workloads.    

CXL
Embedded Memory
Emerging Memories
Hardware Eng.
Memory Systems Eng.
Systems Architecture

Author:

Mark Orthodoxou

VP, Strategic Marketing, Datacenter Product
Rambus

Mark Orthodoxou is the Vice President of Strategic Marketing for Rambus’ Datacenter Products Group. Mark has over 25 years of experience in product management and strategic planning in the semiconductor industry across multiple technology disciplines, including enterprise storage, data center compute, memory subsystems and networking. Mark has evangelized the benefits of serial-attached memory since long before CXL was introduced as a standard and was responsible for the introduction of the first commercially available products in this space. Mark currently sits on the CXL Consortium Marketing Working Group. He has held various leadership positions at Microchip, Microsemi, PMC-Sierra, and IDT.

Mark Orthodoxou

VP, Strategic Marketing, Datacenter Product
Rambus

Mark Orthodoxou is the Vice President of Strategic Marketing for Rambus’ Datacenter Products Group. Mark has over 25 years of experience in product management and strategic planning in the semiconductor industry across multiple technology disciplines, including enterprise storage, data center compute, memory subsystems and networking. Mark has evangelized the benefits of serial-attached memory since long before CXL was introduced as a standard and was responsible for the introduction of the first commercially available products in this space. Mark currently sits on the CXL Consortium Marketing Working Group. He has held various leadership positions at Microchip, Microsemi, PMC-Sierra, and IDT.

 

Maya Preiswerk

Swiss Head of Sanctions
Banque Lombard Odier

Maya Preiswerk

Swiss Head of Sanctions
Banque Lombard Odier

Maya Preiswerk

Swiss Head of Sanctions
Banque Lombard Odier