Macrotrends in innovation are leveraging both software and chips to create the next round of world-changing products. Unlocking the vast potential offered by this innovation model is daunting however. Systemic complexity across all disciplines from silicon to software must be addressed in a holistic way to achieve success. AI applications change over months while chip design can take years, adding to the challenges. Talent shortages also create headwinds. And as more system companies engage in chip design, these headwinds can have a profound impact on the pace of innovation.

Complex chip and system design must be easier to achieve in less time. Sassine Ghazi will discuss several developing strategies that use AI and machine learning techniques to dramatically reduce design time and design risk, opening the opportunity for substantial increases in the pace of innovation.

Many system companies are discovering that optimizing AI/ML SoC devices is a very powerful way to achieve differentiation for specific end-applications. In 2021 the semiconductor industry experienced more rounds of venture capital funding and dollars invested than ever before. What’s more, the investments in new AI companies alonewere higher than all prior yearly totals for all design types combined. Most of these new semiconductor companies targeted specific use cases of AI/ML to achieve aggressive performance, power/heat and other system objectives. Now, system companies are designing their own custom AI/ML SoCs—whether it is hyperscalers, automotive OEMs, edge or telecommunication companies–to address their own unique system-level needs.

Joe Sawicki, executive vice president, IC Siemens EDA, will explain how SoC design solutions are enabling both semiconductor and system companies to efficiently arrive at the global optimization point between power, performance, cost, yield and other factors in their AI/ML hardware designs.  All focused on achieving a holistic, optimized system-level differentiation.

Theoretical metrics such as TOPS frequently fail to predict real-world AI chip performance accurately and to varying degrees, typically overpromise and underdeliver. There is a lot of angst and discussion about this root cause, but an often-overlooked culprit is the clock network, one of the largest networks on an SoC. 

The clock network can be the ultimate gating factor or enabler in data flow on a chip. Data can only move as far as one clock cycle allows. As chips grow larger and approach reticle limits, clock paths also significantly lengthen, further complicating existing clocking problems such as skew and silicon variation (at finer process geometries). An optimized clock network can streamline data flow and raise on-chip interconnect bandwidth.

Standard clock topologies that work well on small chips cannot scale to today’s very large chips. A new approach called intelligent clock networks, delivers an “ideal” clock close to the point of use, simplifying SoC designs and virtually eliminating overhead typically expended for clock distribution. Mo Faisal, the CEO and Founder of Movellus, will examine how intelligent clock networks can usher in a new era of big chip design for AI and HPC applications. Throughout his presentation, Mo will showcase how these new clock network types can help architects reach their architectural goals while generating differentiation in silicon cost and power efficiency in an already crowded market segment.