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Developer Efficiency
Enterprise AI
ML at Scale
Novel AI Hardware
Systems Design
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Alexis Black Bjorlin

VP/GM, DGX Cloud
NVIDIA

Dr. Alexis Black Bjorlin was previously VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

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Alexis Black Bjorlin

VP/GM, DGX Cloud
NVIDIA

Dr. Alexis Black Bjorlin was previously VP, Infrastructure Hardware Engineering at Meta. She also serves on the board of directors at Digital Realty and Celestial AI. Prior to Meta, Dr. Bjorlin was Senior Vice President and General Manager of Broadcom’s Optical Systems Division and previously Corporate Vice President of the Data Center Group and General Manager of the Connectivity Group at Intel. Prior to Intel, she spent eight years as President of Source Photonics, where she also served on the board of directors. She earned a B.S. in Materials Science and Engineering from Massachusetts Institute of Technology and a Ph.D. in Materials Science from the University of California at Santa Barbara.

Author:

Marshall Choy

SVP, Product
SambaNova Systems

Marshall Choy is Senior Vice President of Product at SambaNova Systems and is responsible for product management and go-to-market operations.  Marshall has extensive experience leading global organizations to bring breakthrough products to market, establish new market presences, and grow new and existing lines of business.  Marshall was previously Vice President of Product Management at Oracle until 2018.  He was responsible for the portfolio and strategy for Oracle Systems products and solutions.  He led teams that delivered comprehensive end-to-end hardware and software solutions and product management operations.  Prior to joining Oracle in 2010 when it acquired Sun Microsystems, he served as Director of Engineered Solutions at Sun.  During his 11 years there, Marshall held various positions in development, information technology, and marketing. 

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Marshall Choy

SVP, Product
SambaNova Systems

Marshall Choy is Senior Vice President of Product at SambaNova Systems and is responsible for product management and go-to-market operations.  Marshall has extensive experience leading global organizations to bring breakthrough products to market, establish new market presences, and grow new and existing lines of business.  Marshall was previously Vice President of Product Management at Oracle until 2018.  He was responsible for the portfolio and strategy for Oracle Systems products and solutions.  He led teams that delivered comprehensive end-to-end hardware and software solutions and product management operations.  Prior to joining Oracle in 2010 when it acquired Sun Microsystems, he served as Director of Engineered Solutions at Sun.  During his 11 years there, Marshall held various positions in development, information technology, and marketing. 

AI Hardware Summit attendees are invited to attend the an extended networking session where they can meet attendees from across both events. The Meet & Greet is a perfect opportunity to reconnect with peers, expand your network, and discuss the state of ML across the cloud-edge continuum!

Chip Design
Developer Efficiency
Edge AI
Enterprise AI
ML at Scale
NLP
Novel AI Hardware
Systems Design
Data Science
Hardware Engineering
Software Engineering
Strategy
Systems Engineering

Author:

Colin Murdoch

Chief Business Officer
DeepMind

Decades of international commercial experience and deep technical expertise mean Colin is uniquely placed to ensure DeepMind’s cutting-edge research benefits as many people as possible. As Chief Business Officer of DeepMind, he oversees a wide-range of teams including Applied, which applies research breakthroughs to Google products and infrastructure used by billions of people. He also helps drive the growth of DeepMind, building and leading critical functions including finance and strategy and leading external and commercial partnerships. Originally an electronics and software engineer, he has held senior positions at both start-ups and global companies such as Thomson Reuters, helping them solve their own complex, mission-critical, real-world challenges.

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Colin Murdoch

Chief Business Officer
DeepMind

Decades of international commercial experience and deep technical expertise mean Colin is uniquely placed to ensure DeepMind’s cutting-edge research benefits as many people as possible. As Chief Business Officer of DeepMind, he oversees a wide-range of teams including Applied, which applies research breakthroughs to Google products and infrastructure used by billions of people. He also helps drive the growth of DeepMind, building and leading critical functions including finance and strategy and leading external and commercial partnerships. Originally an electronics and software engineer, he has held senior positions at both start-ups and global companies such as Thomson Reuters, helping them solve their own complex, mission-critical, real-world challenges.

Author:

Cade Metz

Technology Correspondent
New York Times

Cade Metz is a reporter with The New York Times, covering artificial intelligence, driverless cars, robotics, virtual reality, and other emerging areas. Genius Makers is his first book. Previously, he was a senior staff writer with Wired magazine and the U.S. editor of The Register, one of Britain’s leading science and technology news sites.

A native of North Carolina and a graduate of Duke University, Metz, 48, works in The New York Times’ San Francisco bureau and lives across the bay with his wife Taylor and two daughters.

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Cade Metz

Technology Correspondent
New York Times

Cade Metz is a reporter with The New York Times, covering artificial intelligence, driverless cars, robotics, virtual reality, and other emerging areas. Genius Makers is his first book. Previously, he was a senior staff writer with Wired magazine and the U.S. editor of The Register, one of Britain’s leading science and technology news sites.

A native of North Carolina and a graduate of Duke University, Metz, 48, works in The New York Times’ San Francisco bureau and lives across the bay with his wife Taylor and two daughters.

2022 Sample Attendee List

Graphcore's Intelligence Processing Unit (IPU), built on its unique wafer-on-wafer technology architecture, enables innovators across all industries to undertake breakthrough research with the power of AI compute. To deliver what Graphcore believes will be the standard for machine intelligence compute, it follows a continuous integration (CI) and continuous delivery (CD) process to ensure incremental code changes are delivered quickly and reliably to production. In this workshop, Graphcore will share how it’s using Synopsys formal verification solutions throughout the CI/CD process to deliver bug-free silicon.  Workshop topics include:

  • An introduction to Sequential Equivalence Checking (SEQ) and Formal Testbench Analyzer (FTA) applications, part of Synopsys VC Formal
  • Graphcore’s formal verification deployment to maximize engineering productivity
  • How formal is modified for CI and CD
  • Strategies Graphcore employed to overcome reproducibility challenges at the CI stage

 

Hardware Engineer workshop are restricted to hardware engineers and architects, and software designers from companies interested in learning how to design and deploy ML onto hardware platforms.

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a hardware or software engineer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Chip Design
Novel AI Hardware
Systems Design
Hardware Engineering
Systems Engineering

Author:

Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

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Manish Pandey

Fellow & VP, R&D
Synopsys

Manish Pandey is Vice President R&D and Fellow at Synopsys, and an Adjunct Professor at Carnegie Mellon University. He completed his PhD in Computer Science from Carnegie Mellon University and a B. Tech. in Computer Science from the Indian Institute of Technology Kharagpur. He currently leads the R&D teams for formal and static technologies, and machine learning at Synopsys. He previously led the development of several static and formal verification technologies at Verplex and Cadence which are in widespread use in the industry. Manish has been the recipient of the IEEE Transaction in CAD Outstanding Young author award and holds over two dozen patents and refereed publications.

Author:

Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

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Anthony Wood

Formal Verification Lead
Graphcore

Anthony has held a number of a design and verification roles working on CPUs, GPUs and IPUs at Infineon, Xmos, Imagination and Graphcore.  At Imagination he was head of verification for the high-end GPU cores.  At Graphcore his responsibilities include leveraging formal verification techniques throughout the silicon team; reducing delivery timescales through Continuous Delivery; and working to ensure verification disciplines are adopted for DFT.  He strives to find ways of improving the productivity of silicon engineers and of course he agonises about potential verification holes.

State-of-the-art large language models (LLMs) are empowering organizations to unlock the most critical insights in their unstructured data. Despite the opportunities, the cost and complexity of developing these models internally makes them impractical for most organizations to develop on their own. SambaNova overcomes these challenges with production-ready, pre-trained LLMs delivered through a full-stack solution, which can be further adapted through unlimited fine-tuning or pre-training within an organization’s own environment. In this workshop, we will showcase prototyping solutions for enterprise semantic search, legal compliance analysis, and call center service analysis, built on top of pretrained LLMs available through SambaNova Dataflow-as-a-Service. This is followed by live trials on the demo to showcase the exciting potential of large language models.

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs. 

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Developer Efficiency
NLP
Novel AI Hardware
Data Science
Software Engineering

Author:

Jian Zhang

Director, Machine Learning
SambaNova Systems
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Jian Zhang

Director, Machine Learning
SambaNova Systems

Deploying a neural network on an embedded solution requires more than compiling a trained model. Join us to discuss the IP and tooling available from Cadence that allow architects to start with a neural network model, run through quantization and partitioning mapping to a configurable embedded target, simulating the design to get performance data (both cycle and energy), and iterating through design optimizations to reach an optimal implementation. Our experts will give a technical walkthrough of the tools, features, supported frameworks, and infrastructure available to both software and silicon designers.

Hardware Engineer workshop are restricted to hardware engineers and architects, and software designers from companies interested in learning how to design and deploy ML onto hardware platforms.

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a hardware or software engineer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

 

Chip Design
Edge AI
Novel AI Hardware
Hardware Engineering

Author:

Ade Bamidele

Design Engineering Architect
Cadence Design Systems

Ade is an Architect in the Tensilica Central Applications Team. Ade focuses on the optimization and acceleration of imaging and vision algorithms on Vision and AI DSP and engines. He has over 15 years of experience in the R&D and optimization of computer vision and pattern recognition algorithms on vision and embedded devices. Ade graduated from University College London in 2006 with a Doctoral in Electronics Engineering and Thesis focusing on Computational Visual Attention.

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Ade Bamidele

Design Engineering Architect
Cadence Design Systems

Ade is an Architect in the Tensilica Central Applications Team. Ade focuses on the optimization and acceleration of imaging and vision algorithms on Vision and AI DSP and engines. He has over 15 years of experience in the R&D and optimization of computer vision and pattern recognition algorithms on vision and embedded devices. Ade graduated from University College London in 2006 with a Doctoral in Electronics Engineering and Thesis focusing on Computational Visual Attention.

Author:

Michael Hubrig

Sr Design Engineering Architect
Cadence Design Systems

Michael is Sr. Architect in the Tensilica Central Applications Team. His team provides deep technical support for Vision and AI DSP and engines. Michael has 20 years of experience porting imaging and vision algorithms to DSP platforms.

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Michael Hubrig

Sr Design Engineering Architect
Cadence Design Systems

Michael is Sr. Architect in the Tensilica Central Applications Team. His team provides deep technical support for Vision and AI DSP and engines. Michael has 20 years of experience porting imaging and vision algorithms to DSP platforms.

Author:

Rohan Darole

Sr Principal Design Engineer
Cadence Design Systems

Rohan Darole is a ML Product Specialist at Cadence TIP (Tensilica IP Group). He received his Master’s in Computer Science from SUNY-UB, Buffalo, NY. Rohan is leading a team of application engineers responsible for definition, realization, and customer engagements of Tensilica AI MAX Product Family. Previously he has worked on CV/ML Acceleration with Vision DSPs, Imaging (ISP) & Video Codecs SW Development.

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Rohan Darole

Sr Principal Design Engineer
Cadence Design Systems

Rohan Darole is a ML Product Specialist at Cadence TIP (Tensilica IP Group). He received his Master’s in Computer Science from SUNY-UB, Buffalo, NY. Rohan is leading a team of application engineers responsible for definition, realization, and customer engagements of Tensilica AI MAX Product Family. Previously he has worked on CV/ML Acceleration with Vision DSPs, Imaging (ISP) & Video Codecs SW Development.

During this workshop, attendees will be updated on the state of the art in computer vision use cases and learn how to build deep learning models for object detection, while improving model performance. Atos' expert host will provide best practices on team organization to facilitate success. Finally, attendees will learn how to implement an engineering strategy - build a project template & data versioning, experiment tracking & feedback, leverage testing & boost model promotion.

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs. 

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Developer Efficiency
Edge AI
Novel AI Hardware
Data Science
Software Engineering

Author:

Ashwin Sakhare

Senior Data Scientist, Atos zData
Atos

Ashwin Sakhare, PhD is a Senior Data Scientist at Atos zData, a leading AI and Data Science firm. Ashwin leverages over a decade of industry and research experience to solve key business challenges through novel product development and data-driven machine learning approaches. He is a computer vision expert and has delivered AI and machine vision solutions to clients across a broad range of application domains. He has a strong healthcare industry background, where he led the ideation, design, and development of AI products. Ashwin holds a BS in Biomedical Engineering from North Carolina State University and a MS and PhD in Biomedical Engineering from the University of Southern California.

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Ashwin Sakhare

Senior Data Scientist, Atos zData
Atos

Ashwin Sakhare, PhD is a Senior Data Scientist at Atos zData, a leading AI and Data Science firm. Ashwin leverages over a decade of industry and research experience to solve key business challenges through novel product development and data-driven machine learning approaches. He is a computer vision expert and has delivered AI and machine vision solutions to clients across a broad range of application domains. He has a strong healthcare industry background, where he led the ideation, design, and development of AI products. Ashwin holds a BS in Biomedical Engineering from North Carolina State University and a MS and PhD in Biomedical Engineering from the University of Southern California.

Developer workshops are restricted to machine learning practitioners from research institutions and enterprises who are interested in learning how to port code onto novel AI platforms and want to get hands-on access to hardware and SDKs. 

Workshops are application only and subject to eligibility and availability. The workshops are free, and lunch, shared networking sessions, and access to the Meet and Greet function and keynote is included in the developer pass. If you're a machine learning engineer / AI application developer, please apply using the form in the registration section of the website or by emailing [email protected]. There are approximately 30 spaces available.

Developer Efficiency
Novel AI Hardware
Data Science
Software Engineering
Host

Author:

Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

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Jeff Boudier

Product Director
Hugging Face

Jeff Boudier is a product director at Hugging Face, creator of Transformers, the leading open-source NLP library. Previously Jeff was a co-founder of Stupeflix, acquired by GoPro, where he served as director of Product Management, Product Marketing, Business Development and Corporate Development.

Author:

Régis Pierrard

Machine Learning Engineer
HuggingFace
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Régis Pierrard

Machine Learning Engineer
HuggingFace

Author:

Philipp Schmid

Tech Lead
HuggingFace
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Philipp Schmid

Tech Lead
HuggingFace